1. Field of the Invention
The present invention relates to signal quality in chip packages, and more specifically to reducing plating stubs reflections and resonance in high-frequency chip packages.
2. Background of the Related Art
An integrated circuit (IC), also commonly referred to as a “microchip” or “chip,” is an electronic circuit comprising miniaturized semiconductor devices formed in a semiconductor substrate. Many copies of a chip may be formed on a large semiconductor wafer and then cut into individual chips, which may be interchangeably referred to in the art as “die chips” or “dies”. However, semiconductor materials such as silicon are typically brittle, and chips made this way are fragile. Therefore, an individual die chip is commonly packaged on a carrier, referred to as a “chip package” or simply “package.” The chip package protects the chip and provides an electrical and mechanical interface between the chip and a printed circuit board (PCB) such as a computer motherboard.
Electrical connections between a die chip and the package substrate may be made by wirebonding. Wirebonding is a process known in the art by which a very fine wire is connected from a bond pad on the chip to corresponding signal pathways (“traces”) on a package substrate. Bond wires are typically formed of a highly conductive material, such as platinum, copper, aluminum alloys, doped gold, or other precious metal. A package in which a die chip is connected to the substrate by wirebonding may be referred to as a “wirebond package.” The traces on the substrate extend from the location of bonding with the wirebond to signal interconnects elsewhere on the substrate.
The signal interconnects on one layer of the substrate may be electrically connected to signal interconnects on another layer of the substrate using plated through-hole connections known as “vias.” Thus, for example, the signal interconnects on the face to which the chip is mounted may provide a connection between a first face of the substrate and corresponding pins of a pin grid array (PGA) or to corresponding balls of a ball grid array (BGA) on the opposing face of the substrate. The PGA or BGA may then be placed in contact with a corresponding pattern of electrical contacts on the PCB, such as a motherboard, to which the chip package is subsequently secured.
Signal traces are typically formed of commonly available materials, such as copper, that are relatively affordable and have sufficient electrical conductivity. Materials having improved electrical conductivity, including precious metals such as platinum and gold, may then be selectively applied to the substrate at locations where the expense of such materials is warranted. For example, platinum may be applied at locations along the signal traces where bond wires are to be connected. Gold is often used in the formation of signal interconnects.
These electrically conductive materials are usually applied by electroplating. In the electroplating process, a voltage is applied at or near the periphery of the package substrate, which results in open plating stubs extending from the signal interconnects to or near the periphery of the substrate. Plating stubs may hinder signal performance of the package if left intact due to reflections in the open stubs at the high operational frequencies of modern chips. A quarter-wave length resonance is particularly detrimental in high speed data transmissions.